Plasma display panel

ABSTRACT

The invention is a plasma display panel capable of stabilizing the addressing characteristics. A barrier rib is formed by longitudinal barrier ribs portion orthogonal to the scan electrodes and sustain electrodes on the front substrate, and side barrier rib portions crossing with these longitudinal barrier rib portions, to form cell spaces and form interstice portions between the cell spaces, and priming electrodes for producing a discharge between the front substrate and the rear substrate within the interstice portions are formed. Stable priming discharge is produced with certainty by the scan electrode and the priming electrode, hence decreasing the discharge time lag at the time of addressing and stabilizing the addressing characteristics.

TECHNICAL FIELD

The present invention relates to a plasma display panel for use in awall-hung TV or a large-screen monitor.

BACKGROUND ART

In a typical AC-type surface-discharge alternating-current plasmadisplay panel, a front substrate made of glass where scan electrodes andsustain electrodes for performing a surface discharge are arranged and arear substrate made of glass where data electrodes are arranged aredisposed so that the former and latter electrodes are arranged oppositeeach other in parallel to form a matrix with a discharge space between,and the outer periphery is sealed by sealing material such as glassfrit. Discharge cells sectioned by barrier ribs are provided between thesubstrates and a phosphor layer is formed on the discharge cells betweenthese barrier ribs. In the thus-constituted plasma display panel, gasdischarges an ultraviolet light and this ultraviolet light excites Red,Green, and Blue phosphors, hence carrying out color display (refer toJapanese Patent Laid-Open No. 2001-195990).

In this plasma display panel, one field is divided into a plurality ofsub-fields and gradation is displayed by driving a combination of thelight emitting sub-fields. Each sub-field comprises a reset period, anaddress period, and a sustain period. In order to display image data,the signal waveforms respectively different in the reset period, theaddress period, and the sustain period are applied to the respectiveelectrodes.

In the reset period, for example, a positive pulse voltage is applied toall the scan electrodes, and a necessary wall charge is accumulated onthe protective film and the phosphor layer on a dielectric layercovering the scan electrode and the sustain electrode.

In the address period, all the scan electrodes are scanned bysequentially applying a negative scan pulse there, and in the case wherethere is display data, when a positive data pulse is applied to the dataelectrode during the scan of the scan electrodes, a discharge occursbetween the scan electrode and the data electrode and a wall charge isformed on the surface of the protective film on the scan electrode.

In the next sustain period, a voltage enough to support a dischargebetween the scan electrode and the sustain electrode is applied for apredetermined period. Through this measure, a plasma discharge isgenerated between the scan electrode and the sustain electrode, and thephosphor layer is excited to emit light for the predetermined period. Inthe discharge space where the data pulses were not applied during theaddress period, no discharge occurs, and excitation and light-emissionof the phosphor layer does not occur.

In the thus configured plasma display panel, there has been a problemthat writing operation is made unstable because of a large dischargetime lag in the discharge during the address period or else too muchtime is taken for the address period because the writing time is setlonger in order to completely perform the writing operation. In order tosolve the above problem, there has been proposed a panel in which anauxiliary discharge electrode is provided on the front substrate, andthe auxiliary discharge within the surface of the front substrategenerates a priming discharge which decreases the discharge time lag,and a driving method for this panel (refer to Japanese Patent Laid-OpenNo. 2002-297091).

In this plasma display panel, however, there arises the problem thatwhen the number of lines is increased as screen resolution becomesfiner, the address time must be made longer, and accordingly it isnecessary to decrease the time for the sustain period, and it isdifficult to obtain brightness. Further, also in the case of increasingthe partial pressure of xenon in order to increase the brightness andefficiency, there is the problem that the discharge starting voltageincreases and discharge time lag is increased, hence to deteriorate theaddress characteristic. Since the address characteristics are muchaffected by the manufacturing process, it is necessary to decrease thedischarge time lag during addressing to shorten the address time andlessen the effects of random production disuniformities.

With respect to this request, the conventional plasma display panelperforming the priming discharge within the front substrate has aproblem of failing to shorten the discharge time lag fully duringwriting, there is the problem that there is a tendency for wrongdischarge in some panels because the margin of error for the auxiliarydischarge is small, and further the problem that crosstalk is generatedas the result of supplying more priming particles than is necessary forpriming to adjacent discharge cells. A certain distance between theelectrodes is necessary in order to realize the stable auxiliarydischarge for supplying the priming particles. Therefore, the auxiliarydischarge cell becomes larger to accommodate the auxiliary dischargewithin the front substrate, and a finer resolution panel cannot beachieved.

DISCLOSURE OF THE INVENTION

Taking the above problems into consideration, an object of the presentinvention is to provide a plasma display panel capable of stabilizingthe address characteristics even in the case of a finer-pitch panel.

In order to achieve the above object, a plasma display panel of theinvention comprises first electrodes and second electrodes arranged on afirst substrate in parallel and alternating with each other and coveredwith a dielectric layer, third electrodes arranged on a second substratedisposed facing the first substrate with a discharge space therebetweenand intersecting the axes of the first electrodes and the secondelectrodes, and fourth electrodes arranged on the second substrate forproducing a discharge between fourth electrodes and the first electrodesor between fourth electrodes and the second electrodes.

According to this structure, since a priming discharge is verticallyperformed on the first substrate and the second substrate, it ispossible to realize a plasma display panel superior in addresscharacteristic by downsizing an auxiliary discharge cell, thus enablinga finer-pitch panel and making priming discharge stable.

Further, barrier ribs for sectioning a plurality of discharge cellsformed by the first electrodes, the second electrodes, and the thirdelectrodes may be provided on the second substrate and a phosphor layermay be provided on the discharge cells. Further, it is preferable thatthe barrier rib consists of longitudinal barrier rib portions extendingorthogonal to the first electrodes and the second electrodes and sidebarrier rib portions crossing these longitudinal barrier rib portions soas to form interstice portions, and that the fourth electrode is formedon the second substrate of the interstice portion.

With the above structure, a stable priming discharge can be assuredlygenerated between the first substrate and the second substrate in theinterstice portion, the priming particles can be supplied to theadjacent discharge cell in the same row, and the discharge time lag at atime of addressing can be decreased irrespective of the materialcharacteristics of the phosphor layer, thereby stabilizing the addresscharacteristic.

Further, the interstice portion may be continuously formed by theadjacent side barrier rib portions in parallel with the first electrodeand the second electrode. Therefore, the priming discharge can bediffused in the interstice portion, thereby stabilizing the priming tothe respective discharge cells.

Further, a light absorption layer may be formed on the first substrateat a position corresponding to the discharge space formed by the fourthelectrode. Therefore, the light absorption layer can absorb the lightemission in the interstice portion and prevent deterioration of contrastby the priming discharge produced within the interstice portion.

Further, it is preferable that the light absorption layer is formed on asurface of the first substrate facing the discharge space. Therefore,the light emission by the priming discharge is confined to theinterstice portion, thereby further improving the contrast.

The fourth electrode may be formed at a position nearer to the dischargespace than the third electrode, the discharge voltage of the primingdischarge within the interstice portion can be made less than thedischarge voltage of the discharge cell using the third electrode, andprior to the address discharge of the discharge cell, it is possible toproduce a stable priming discharge.

The third electrode may be formed at a position nearer to the dischargespace than the fourth electrode. Accordingly, the address dischargevoltage generated by the third electrode can be decreased.

Further, when a scan pulse is applied, a priming discharge is producedbetween the first electrode where the scan pulse is applied and thefourth electrode. Therefore, it is possible to produce, when mostnecessary for the discharge cell, an optimum priming discharge for thepurpose of decreasing the discharge time lag at a time of addressing,and obtain more stable address characteristics.

Further, it is preferable that the first electrodes and the secondelectrodes are arranged in alternating lines. Therefore, since theelectrodes of the adjacent portions of the discharge cells in the columndirection become the same potential, the charge and dischargeelectricity consumed between the adjacent cells is decreased and theelectricity is reduced.

Further, the fourth electrode is formed on the second substratecorresponding to the portion where the first electrodes applied the scanpulse are adjacent to each other. Therefore, a wrong discharge occurringbetween the second electrode and the fourth electrode can be preventedand stable operation can be performed.

Further, it is preferable that a discharge area for inducing a dischargebetween the first electrode on the first substrate and the fourthelectrode on the second substrate is formed in a portion outside thedisplay area. According to this structure, it is possible to decreasethe time lag of the priming discharge itself which is produced withinthe interstice portion by discharging in a peripheral discharge area,realize higher-speed addressing, and shorten the address time.

Further, it is preferable that the fourth electrode for producing adischarge between the first substrate and the second substrate producesa discharge by applying a positive voltage pulse during the addressperiod and further that the positive voltage value to be applied to thefourth electrode during the address period is set larger than thevoltage value to be applied to the third electrode during the addressperiod. Therefore, it is possible to produce a priming discharge moreassuredly within the interstice portion.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view showing a plasma display panelaccording to the embodiment 1 of the invention.

FIG. 2 is a plan view schematically showing the array of electrodes onthe front substrate of the same plasma display panel.

FIG. 3 is a perspective view schematically showing the rear substrate ofthe same plasma display panel.

FIG. 4 is a plan view schematically showing the rear substrate of thesame plasma display panel.

FIG. 5 is a cross sectional view cut off along the line A-A of FIG. 4.

FIG. 6 is a cross sectional view cut off along the line B-B of FIG. 4.

FIG. 7 is a cross sectional view cut off along the line C-C of FIG. 4.

FIG. 8 is a waveform view showing one example of a driving waveform foroperating the same plasma display panel.

FIG. 9 is a characteristic view showing one example of thecharacteristic of a discharge time lag in the same plasma display panel.

FIG. 10 is a characteristic view showing one example of the statisticaltime lag in a discharge according to the priming voltage in the sameplasma display panel.

FIG. 11 is a plan view showing one example of a scan electrode drawn outfrom the same plasma display panel.

FIG. 12 is a cross sectional view of the same plasma display panel witha second light absorption layer provided therein.

FIG. 13 is a plan view showing the structure of an important portion ofthe plasma display panel according to the embodiment 2 of the invention.

FIG. 14 is a cross sectional view showing the plasma display panelaccording to the embodiment 3 of the invention.

FIG. 15 is a cross sectional view showing the plasma display panelaccording to the embodiment 4 of the invention.

FIG. 16 is a plan view showing the structure of an important portion ofthe plasma display panel according to the embodiment 5 of the invention.

FIG. 17 is a plan view showing the structure of the rear substrate ofthe plasma display panel according to the embodiment 6 of the invention.

FIG. 18 is a cross sectional view showing the plasma display panelaccording to the embodiment 7 of the invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Hereinafter, the plasma display panel according to the embodiments ofthe invention will be described by using the drawings.

[Embodiment 1]

FIG. 1 is a cross sectional view showing the plasma display panelaccording to the embodiment 1 of the invention, FIG. 2 is a plan viewschematically showing the array of electrodes on the front substratethat is the first substrate, FIG. 3 is a perspective view schematicallyshowing the rear substrate that is the second substrate, and FIG. 4 is aplan view of the rear substrate that is the second substrate. Further,FIG. 5, FIG. 6, and FIG. 7 are cross sectional views respectively cutoff along the A-A line, the B-B line, and the C-C line of FIG. 4.

As shown in FIG. 1, a front substrate 1 made of glass that is the firstsubstrate and a rear substrate 2 made of glass that is the secondsubstrate are arranged facing each other with a discharge space 3between them, and as a gas which radiates ultraviolet light when adischarge is applied, neon, xenon, or a mixture of them is charged inthe discharge space 3. On the front substrate 1, an electrode groupincluding pairs of scan electrodes 6 that are the strip-shaped firstelectrodes and pairs of sustain electrodes 7 that are the strip-shapedsecond electrodes, covered with a dielectric layer 4 and a protectivefilm 5, are arranged in parallel with each other. The scan electrode 6and the sustain electrode 7 respectively comprise transparent electrodes6 a and 7 a and metal buses 6 b and 7 b made of silver or the like forincreasing the conductivity, overlapping the transparent electrodes 6 aand 7 a.

Further, as illustrated in FIG. 2, the two scan electrodes 6 and the twosustain electrodes 7 are alternatively arranged in a sequence of scanelectrode 6-scan electrode 6-sustain electrode 7-sustain electrode 7 ,and a light absorption layer 8 made of black material is respectivelyprovided between the scan electrodes and between the sustain electrodes7.

On the other hand, the structure of the rear substrate 2 will bedescribed by using FIG. 1, FIGS. 3 to 7. On the rear substrate 2, aplurality of strip-shaped data electrodes 9 that are the thirdelectrodes are arranged in parallel with one another but crossing thescan electrodes 6 and the sustain electrodes 7 at right angles. Further,barrier ribs 10 for dividing several discharge cells 11 each formed by ascan electrode 6, a sustain electrode 7, and a data electrode 9 areformed on the rear substrate 2, and phosphor layers 12 formed for eachof the discharge cells 11 divided by these barrier ribs 10 are provided.The barrier rib 10 is formed by longitudinal barrier rib portions 10 aextending orthogonal to the scan electrodes 6 and the sustain electrodes7 provided on the front substrate 1, namely, parallel to the dataelectrodes 9, and side barrier rib portions 10 b crossing with thelongitudinal barrier ribs 10 a so to form the discharge cells 11 as wellas to form an interstice portion 13 between the discharge cells 11. Thelight absorption layer 8 formed on the front substrate 1 is formed at aposition corresponding to the space of the interstice portion 13 formedbetween the side barrier ribs 10 b of the barrier ribs 10.

In the interstice portion 13 of the rear substrate 2, a primingelectrode 14 that is the fourth electrode for generating a dischargebetween the front substrate 1 and the rear substrate 2 within the spaceof the interstice portion 13 is formed orthogonal to the data electrode9, and a priming discharge cell comprises the interstice portion 13. Theinterstice portions 13 are formed continuously in a direction orthogonalto the data electrodes. The priming electrode 14 is formed on thedielectric layer 15 which covers the data electrodes 9, anotherdielectric layer 16 is formed so as to cover the priming electrode 14,and the priming electrode 14 is formed at a position nearer to the spacewithin the interstice portion 13 than the data electrode 9. Further, thepriming electrode 14 is formed only in the portions of the intersticeportion 13 facing the scan electrodes 6 to which a scan pulse isapplied, and one portion of the metal buses 6 b of the scan electrode 6extends to a position facing the interstice portion 13 and is formed onthe light absorption layer 8. Namely, a priming discharge is generatedbetween the metal bus 6 b of adjacent scan electrodes 6 and protrudingtoward the interstice portion 13, and the priming electrode 14 formed onthe rear substrate 2.

Next, a method of displaying image data on the plasma display panel willbe described by using FIG. 8. In a method of driving the plasma displaypanel, one field period is divided into a plurality of sub-fields eachhaving the weight of the luminescent period, and gradation display isproduced by combination of the sub-fields caused to emit light. Eachsub-field is formed by a reset period, an address period, and a sustainperiod.

FIG. 8 shows one example of the driving waveform for driving the aboveplasma display panel. In the reset period shown in FIG. 8, in thepriming discharge cell where a priming electrode Pr (the primingelectrode 14 in FIG. 1) has been formed, resetting is performed betweenthe scan electrode Yn, one portion of which protrudes into theinterstice portion (the interstice portion 13 in FIG. 1), and thepriming electrode Pr. In the following address period, as illustrated inFIG. 8, a positive potential is always applied to the priming electrodePr. Therefore, in the priming discharge cell, when a scan pulse SPn isapplied to the scan electrode Yn, a priming discharge occurs between thepriming electrode Pr and the scan electrode Yn. Accordingly, thedischarge time lag at a time of addressing in the n^(th) discharge cellis decreased according to this priming discharge, hence to stabilize theaddress characteristic.

Next, though the scan pulse SPn+1 is applied to the scan electrode Yn+1of the (n+1)^(th) discharge cell, since the priming discharge hasoccurred just before at this time, the discharge time lag at a time ofaddressing also becomes smaller in the (n+1)^(th) discharge cell.Although only the description of the driving sequence of certain onefield has been made here, the operation principle in the othersub-fields is the same.

Here, in the driving waveform shown in FIG. 8, a priming discharge canbe produced steadily by applying a positive voltage to the primingelectrode Pr during the address period. It is preferable that thevoltage value Vpr to be applied to the priming electrode Pr is set at alarger value than the data voltage value Vd to be applied to the dataelectrode D (the data electrode 9 of FIG. 1) during the address period.

Further, as long as the voltage value applied to the priming electrodePr during the address period is positive relative to the voltage valueapplied to the priming electrode Pr during the reset period, it may be anegative voltage value relative to the GND (ground) level.

As mentioned above, since the priming discharge occurs when a scan pulseis applied to the scan electrode in the priming discharge cell, it ispossible to generate a priming discharge without fail at a time ofaddressing and decrease the discharge time lag more effectively at atime of addressing. Thus, the priming discharge can be producedassuredly in the interstice portion and the address characteristics canbe made more stable.

In the embodiment, as shown in FIG. 1, FIG. 3, FIG. 4, and FIG. 5, thepriming discharge is vertically produced between the scan electrode 6provided on the front substrate 1 and the priming electrode 14 providedon the rear substrate 2, and this priming electrode 14 crosses the dataelectrodes 9 only in the region of the interstice portion 13.Accordingly, it is possible to produce a priming discharge only in theinterstice portion 13. Therefore, in contrast with the case of producinga priming discharge within the surface of the front substrate 1, it ispossible to restrain the crosstalk generated by supplying more primingparticles than necessary for priming to the adjacent discharge cell 11.

Further, the purpose of using the priming discharge is to stabilize theaddress characteristics when the display screen is given finerresolution. When a priming discharge is produced within the surface ofthe front substrate 1, a certain distance between electrodes isnecessary to get a stable priming discharge, and thus the auxiliarydischarge cell, namely, the priming discharge cell, becomes larger.Because of this, the proportion of the area of all the discharge cellsoccupied by priming discharge cells is increased, hence deterioratingthe brightness of the panel. When a priming discharge is caused to occurin a space other than within the surface of the front substrate 1 whenthe scan pulse is applied, there is the problem that a structureallowing some of the scan electrodes 6 to be wired on the rear substrate2 and allowing extraction of the electrodes is complicated and furtherthere is the problem that it is difficult to assure stability againstthe voltage at that time.

By generating the priming discharge vertically between the scanelectrode 6 provided on the front substrate 1 and the priming electrode14 provided on the rear substrate 2, the priming discharge cell can bemade smaller, and a plasma display panel superior in addressingcharacteristics and with improved brightness can be realized even if thepanel is made with finer resolution.

As mentioned in this embodiment, the priming electrode 14 is positionednearer to the discharge space 3 where priming discharge is generatedthan the data electrode 9. Therefore, the distance between the primingelectrode 14 and the scan electrode 6 becomes smaller, this decreasesthe discharge staring voltage, and the priming discharge can begenerated in the interstice portion 13 with a low voltage. Further,since this embodiment allows easily generation of the priming dischargeearlier than the address discharge, the address characteristic can beimproved.

Further, the priming electrode 14 is provided only in the regioncorresponding to the adjacent electrodes 6. Therefore, a primingdischarge occurs only between the scan electrode 6 and the primingelectrode 14, and a wrong discharge between the priming electrode 14 andthe sustain electrode 7 can be prevented.

FIG. 9 is a graph of one example of the discharge time lagcharacteristic of the plasma display panel, the horizontal axisindicating the time. FIG. 9A shows the case where there is no primingdischarge, FIG. 9B and FIG. 9C show the case where there is a primingdischarge, FIG. 9B shows characteristics of the cell of the Yn^(th) scanelectrode, and FIG. 9C shows the characteristic of the cell of the(Yn+1)^(th) scan electrode. Further, FIG. 10 shows the statistical timelag time of a discharge after application of the voltage Vpr to thepriming electrode Pr in the cases of the cell of the Yn^(th) scanelectrode and the cell of the (Yn+1)^(th) scan electrode.

In FIG. 9, the letter a indicates a light-emission output waveform, theletter b indicates a voltage waveform applied to the scan electrode, theletter c indicates a probability distribution of discharge, the letter dindicates a light-emission output waveform of priming discharge, and theletter e indicates a light-emission output waveform of writingdischarge. The probability distribution of the discharge of c indicatesa discharge time lag. Comparing FIGS. 9A, (b), and (c), when there ispriming discharge as shown in FIGS. 9B and (c), the probabilitydistribution of the discharge is sharper than in the case where there isno priming discharge in FIG. 9A. Accordingly, it is found that thedischarge time lag is small. Because there is a priming discharge whenthe scan pulse is applied to the scan electrode Yn of the Yn^(th)discharge cell, the discharge time lag in the Yn^(th) cell is ratherlarge, but since the (Yn+1)^(th) discharge cell has been alreadyaffected by the priming discharge, it is possible to make the dischargetime lag of the (Yn+1)^(th) discharge cell extremely small

On the other hand, as illustrated in FIG. 10, with increase of thepriming voltage Vpr, it is found that the statistic time lag of thedischarge is greatly reduced, especially in the Yn^(th) cell which isperforming the priming discharge when the scan pulse is applied. Thestatistic time lag of the discharge when there is no priming dischargeis about 2400 ns, which shows that the discharge time lag can beextremely improved according to the invention.

FIG. 11 is a plan view showing an example of drawing the scan electrode6. FIG. 11A shows an example where a metal bus line 6 b of the scanelectrode 6 is made to protrude toward the data electrode 9, andprotruding portions 20 serving as priming scan electrode portions 22 areformed. FIG. 11B shows an example of providing a connection portion 21in a non-display area of the metal bus line 6 b, hence to be connectedwith the scan electrode portion 22 for priming. In FIG. 11, a slantedportion of the metal bus line 6 b is used for removing the electrode.Though the priming discharge can be surely and stably performed in anycase, it can be performed with still greater certainty by providing thescan electrode portion 22 for priming continuously within the intersticeportion 13 where the priming discharge is produced, as shown in FIG.11B.

The interstice portion 13 for producing the priming discharge iscontinuously formed in a direction orthogonal to the data electrodes 9.Therefore, it is possible to decrease disuniformity of the primingdischarge produced within the long interstice portion 13 along thepriming electrode 14.

Further, in the embodiment, the rectangle discharge cell 11 is formed byproviding barrier rib 10 comprising the longitudinal barrier rib 10 aand the side barrier rib 10 b on the rear substrate 2 and the intersticeportion 13 is a space formed in parallel with the scan electrode 6 andthe sustain electrode 7. The invention, however, is needless to say notrestricted to the discharge cell of this shape, and can have a dischargecell having a wave-shaped barrier rib.

Further, in the embodiment of the invention, two scan electrodes 6 andtwo sustain electrodes 7 are alternately arranged as illustrated in FIG.2. Therefore, in the discharge cell, the electrodes of the portions inadjacent columns become the same potential, thereby decreasing thedischarge electricity escaping between the adjacent cells and thusreducing the electricity consumption.

Further, in the embodiment of the invention, as illustrated in FIG. 1,on the side of, the front substrate 1, the light absorption layers 8 arerespectively formed between the adjacent scan electrodes 6 and betweenthe adjacent sustain electrodes 7. Therefore, this light absorptionlayer 8 can prevent the light-emission of the priming discharge in theinterstice portion 13 from escaping, hence preventing deterioration incontrast while improving the addressing characteristics.

Further, the plasma display panel as shown in FIG. 12 has the samestructure as that of FIG. 1, and further second light absorption layers23 are provided on the dielectric layer 4 or the protective film 5 andbetween the adjacent scan electrodes 6 and between the sustainelectrodes 7. Therefore, it is possible to improve the contrast further.

Since the light absorption layer 8 or the second light absorption layer23 is thus provided on the front substrate 1 at a position correspondingto the interstice portion 13, the phosphor may enter into the intersticeportion 13 and the formation of the phosphor becomes easy.

In FIG. 1 and FIG. 12, though the light absorption layer 8 is providedalso between the sustain electrodes 7, since no priming discharge occursin this interstice portion 13, it is also possible to form thisinterstice portion without providing the light absorption layer.

[Embodiment 2]

FIG. 13 is a plan view showing the structure of an important portion ofthe plasma display panel according to the embodiment 2 of the invention.In the embodiment 2, a discharge area for inducing a priming dischargebetween the front substrate 1 and the rear substrate 2 within theinterstice portion 13 is provided in the peripheral portion around thedisplay area of the plasma display panel.

It is necessary to produce a priming discharge which itself is stableand without discharge time lag in a method for improving the addressingcharacteristics by such priming discharge. In the embodiment 2, adischarge area for producing an auxiliary discharge which can be astable priming discharge is formed in the peripheral portion of thepanel.

As illustrated in FIG. 13, the metal bus line 6 b of the scan electrode6 corresponding to the priming electrode 14 extends to the peripheralarea around the display area 50 formed by the barrier rib 10 andsimilarly, the priming electrode 14 also extends to, the peripheral areaaround the display area 50. Therefore, areas 17 for auxiliary dischargeof the priming discharge are formed in the peripheral area, and thepriming discharge can be produced stably without discharge time lag dueto the auxiliary discharge produced in this area. Although the examplein the case of producing the discharge between the scan electrodes 6 andthe priming electrode 14 in the auxiliary discharge area 17 shown inFIG. 13, the auxiliary discharge may instead be produced between thescan electrode 6 and the electrode formed in parallel with the dataelectrode 9.

[Embodiment 3]

FIG. 14 is a cross sectional view showing the plasma display panelaccording to the embodiment 3 of the invention. In the embodiment 3, inaddition to the priming electrode 14 formed on the rear substrate 2, apriming electrode 18 is formed in the area corresponding to theinterstice portion 13, between the interstice portion 13 and the frontsubstrate 1. A new voltage waveform other than that of the scanelectrode 6 may be applied to this priming electrode 18, even if itspotential is the same as that of the scan electrode 6. It is possible toproduce a priming discharge within the interstice portion 13 at a higherspeed by forming this electrode structure, hence enabling fasterwriting.

[Embodiment 4]

FIG. 15 is a cross sectional view showing the plasma display panelaccording to the embodiment 4 of the invention. In the embodiment 4, thepriming electrode 14 formed on the side of the rear substrate 2 in theembodiment 1 shown in FIG. 1 is not covered with the dielectric layer 16but exposed to the space of the interstice portion 13.

By exposing the priming electrode 14, it is possible to make a voltagefor the priming discharge at a low voltage.

[Embodiment 5]

FIG. 16 is a plan view showing the structure of an important portion ofthe plasma display panel in the embodiment 5 of the invention. In theembodiment 5, the transparent electrodes 6 a and 7 a for forming thescan electrode 6 and the sustain electrode 7 are both formed in T-shape,and one of the transparent electrodes 6 a of the scan electrode 6 isprotruded from the metal bus line 6 b, this protrusion being theelectrode portion 6 c facing the priming electrode 14. By devising theshape of the electrode as mentioned above, it is possible to control thesize of the priming discharge.

[Embodiment 6]

FIG. 17 is a plan view showing the structure of the rear substrate ofthe plasma display panel in the embodiment 6 of the invention. In theembodiment 6, the priming electrodes 19 are formed on the same surfaceas the data electrodes 9, extending under the longitudinal barrier rib10 a of the barrier rib 10. By forming the panel in this way, it ispossible to eliminate crossing of the data electrode 9 and the primingelectrode 19, thereby improving the ability of the data electrode 9 andthe priming electrode 19 to withstand high voltage, and restraining thegeneration of useless electricity at the crossing the data electrode 9and the priming electrode 19.

[Embodiment 7]

FIG. 18 is a cross sectional view showing the plasma display panelaccording to the embodiment 7 of the invention. As shown in FIG. 18, inthe embodiment 7, the structure of a data electrode 33 that is the thirdelectrode and a priming electrode 31 that is the fourth electrode whichare formed on the rear substrate 2 is different from the structurementioned in embodiment 1.

Namely, in embodiment 7, the priming electrode 31 is formed on the rearsubstrate 2 at first, a dielectric layer 32 is provided to cover thepriming electrode 31, and a data electrode 33 is provided on thedielectric layer 32. Further, the data electrode 33 is covered by adielectric layer 34 that becomes the groundwork for forming the barrierrib, and the barrier rib 35 is formed on the dielectric layer 34. Thus,in the embodiment 7, only the structure on the rear substrate 2 isdifferent from the embodiment 1 and the structure of the front substrate1 is the same as that of the embodiment 1.

According to the embodiment 7, the data electrode 33 is formed at aposition nearer to the discharge space 3 than the priming electrode 31.Therefore, it is possible to thin the dielectric layer 34 formed on thedata electrode 33 and lower the voltage of the address discharge,thereby stabilizing the address discharge. The dielectric layer 32formed on the priming electrode 31 is an insulating layer between thepriming electrode 31 and the data electrode 33 and the same layer of anythickness and material sufficient to secure the insulation of both maybe chosen.

As mentioned above, the invention is able to produce with certainty apriming discharge in the interstice portion that is the primingdischarge cell, and so stabilize the addressing characteristics.

INDUSTRIAL APPLICABILITY

Since the plasma display panel according to the invention can produce apriming discharge in a small space assuredly, it can be useful forplasma display panels with high resolution, since it has small dischargetime lag and favorable addressing characteristics.

Reference Numerals in the Drawings

-   1 front substrate-   2 rear substrate-   3 discharge space-   4,15,16,32,34 dielectric layer-   4 protective film-   5 scan electrode-   6 a,7 a transparant electrode-   6 c electrode portion-   7 sutain electrode-   8 light absorption layer-   9,33 data electrode-   10,35 barrier rib-   10 a longitudinal barrier rib portion-   10 b side barrier rib portion-   11 discharge cell-   12 phosphor layer-   13 interstice portion-   14,18,19,31 priming electrode-   17 discharge area-   20 protruding portion-   21 connection portion-   22 scan electrode portion-   23 second light absorption layer-   50 display area

1. A plasma display panel comprising: a first electrode and a secondelectrode arranged on a first substrate parallel with each other andcovered with a dielectric layer; a third electrode arranged on a secondsubstrate facing the first substrate across a discharge space andarranged in a direction crossing the first electrode and the secondelectrode; and a fourth electrode arranged on the second substrate forproducing a discharge between the fourth electrodes and the firstelectrodes or between the fourth electrodes and the second electrodes.2. The plasma display panel according to claim 1, further comprising:barrier ribs for dividing a plurality of discharge cells formed by thefirst electrodes, the second electrodes and the third electrodes intosections on the second substrate, wherein a phosphor layer is providedon the discharge cells.
 3. The plasma display panel according to claim2, wherein the barrier rib is formed by a longitudinal barrier ribportion orthogonal to the first electrode and the second electrode and aside barrier rib portion crossing with the longitudinal barrier ribportion so as to form an interstice portion, wherein the fourthelectrode is formed on the second substrate at the interstice portion.4. The plasma display panel according to claim 3, wherein an intersticeportion is a continuous space formed by the adjacent side barrier ribportions in parallel with the first electrode and the second electrode.5. The plasma display panel according to claim 1, wherein a lightabsorption layer is formed on the first substrate at a positioncorresponding to a discharge space formed by the fourth electrodes. 6.The plasma display panel according to claim 5, wherein the lightabsorption layer is formed on the surface area of the first substratewhere it bounds the discharge space.
 7. The plasma display panelaccording to claim 1, wherein the fourth electrode is formed at aposition nearer to the discharge space than the third electrode.
 8. Theplasma display panel according to claim 1, wherein the third electrodeis formed at a position nearer to the discharge space than the fourthelectrode.
 9. The plasma display panel according to claim 1, whereinwhen a scan pulse is applied, a priming discharge is produced betweenthe first electrode where the scan pulse is applied and the fourthelectrode.
 10. The plasma display panel according to claim 1, wherein apair of first electrodes and a pair of second electrodes are arranged soas to alternate with each other.
 11. The plasma display panel accordingto claim 10 wherein the fourth electrodes is formed on the secondsubstrate corresponding to a portion where the two first electrodesadjoin each other on which a scan pulse are applied.
 12. The plasmadisplay panel according to claim 1, wherein a discharge area forinducing a discharge between the first electrode on the first substrateand the fourth electrode on the second substrate is formed in aperipheral portion outside a display area.
 13. The plasma display panelaccording to claim 1, wherein the fourth electrode for producing adischarge between the first substrate and the second substrate producesthe discharge during an address period.
 14. The plasma display panelaccording to claim 1, wherein the fourth electrode applies a positivevoltage pulse during an address period.
 15. The plasma display panelaccording to claim 14, wherein a value of the positive voltage pulseapplied to the fourth electrode during the address period is set largerthan a voltage value applied to the third electrode during the addressperiod.